A wide variety of memory devices can be used to maintain and store data and instructions for various computers and similar systems, including non-volatile memory devices that do not require power to retain information (e.g., EPROM, EEPROM, and Flash memory).
Memory devices contain memory cells, which store information in the form of binary bit(s) (e.g., logic “0”, “1”, “00”, “01”, “10”, or “11”). This information is retrieved by sensing the state of memory cells, e.g., by sensing current drawn by a memory cell and comparing such current with a reference current. For example, if the sensed current drawn by a memory cell exceeds a reference current, the memory cell's state is considered to be a logic 1; otherwise, the memory cell's state is considered to be a logic 0.
One concern with sensing the state of a memory cell is reduced sensing margin. Improving sensing margin, which is the amount of sensed current/voltage above or below a fixed reference current/voltage, increases the usable lifetime of a memory cell. Sensing margin and the usable lifetime of a memory cell are reduced when a memory cell's characteristics (e.g., threshold voltage) change over time, affecting how data stored in the memory cell is evaluated. For example, if at the beginning of life of a memory cell, current sensed during a read operation of the memory cell exceeds a fixed reference current, the state of the memory cell is considered to be a logic 1. However, if after a period of time, current sensed during a read operation of the memory cell is below the fixed reference current (e.g., due to charge retention), the state of the memory cell is considered to be a logic 0.
Dynamic tracking reference devices can be used to improve sensing margin by reflecting the degree that a memory cell's characteristics have changed over time. However, dynamic tracking reference device performance is limited because dynamic reference device characteristics can differ from memory cell device characteristics, e.g., the sensing margin of a dynamic tracking reference device can differ from the sensing margin of a memory cell. Further, although sensing margin can be improved by utilizing trim bits to reflect individual memory cell characteristics, the use of trim bits increases memory cell programming overhead involved in memory device manufacturing and testing, and increases memory device design complexity.
It is therefore desirable to have systems and methods that improve memory cell sensing margins, reduce overhead involved in memory device manufacturing and testing, and reduce memory device design complexity.